Setting up U-Boot
LX60, LX200, ML605, KC705 U-Boot Installation
(News: U-Boot for the new DC233, with the V3 MMU, is now working fine and checked into the master branch. Work is almost complete with the Linux 2.6.29-smp kernel, with Linux now booting from this updated U-Boot. The kernel on the 'Initialize_MMU_Inside_vmlinux' branch seems to be working fine, and has survived 14 hours of stress testing so far. Plain is to merge this and a few additional branches to the master branch and then move forward to a newer version of the Linux kernel. Summary:
U-Boot is a very popular boot loader; especially within the Embedded Linux community. The U-Boot loader runs on the FPGA boards which are equipped with a Boot Select dip switch, (number 8 on Avnet and ML605 boards, number 1 on KC705), which can select where the memory location for the reset vector (0XFE00,0000) comes from. With the Boot Switch off the board will map the memory at the reset vector to a small block of SRAM located in the I/O block with the UART and Ethernet buffer memory. When the Boot Switch is on the xtfpga boards map the Bootloader area of the Flash Memory (at 0XF800,0000 on Avnet and ML605 boards, at 0xF600,0000 on KC705) to the reset vector at 0xFE00,0000.
What we are going to do here is build a version of U-Boot for your xtfpga board and Variant, install that ELF file into memory with xt-gdb and run U-Boot. Then we are going to download a another copy of this identical program with tftp. The version we are going to download is just the ELF file with the headers and debug information removed. It's just the actual bits that get loaded into memory. For the new V3 MMU the default loadaddr is typically 0x20,0000 and for the older V2 MMU this is in the Linux mapping equivalent, 0xD0200,0000. The default location can be changed by setting the U-Boot 'loadaddr' environment variable or by changing the variable CONFIG_SYS_LOAD_ADDR in the boards U-Boot config file.
Once the virgin copy of the U-Boot program has been loaded into memory, the Flash memory is un-protected and erased, then the memory with the U-Boot program in it is copied to the flash memory and protected. Next you will set Boot Select dip switch on, cycle power on the board, and U-Boot will be accessible via the serial UART at 38400 baud. U-Boot works without any MMU mapping, and should be fine on configurations without an MMU. Only an ethernet and serial interface are required.
Proceedure:
A local port to the Xtensa architecture is now available at linux-xtensa.org. See U-Boot Sources (GIT Summary). Or, to access this tree using git directly, use something like:
$ git clone git://git.linux-xtensa.org/git/u-boot/u-boot-xtensa.git u-boot $ cd u-boot
(Note: This path is subject to change.)
The U-Boot git repository has a branch with a HiFi 2 snapshot made for
the LX200 SMP HiFi 2 Development Board. With this branch you can simply check
out the snapshot_2+SMP branch which includes the binaries which are discussed below:
$ git clone git://git.linux-xtensa.org/git/u-boot/u-boot-xtensa.git u-boot $ cd u-boot $ git branch --track snapshot_2+SMP origin/snapshot_2+SMP $ git checkout snapshot_2+SMP
$ ls -l u-boot u-boot.bin tools/mkimage
-rwxr-xr-x 1 piet tensilica 45016 2009-12-07 19:40 tools/mkimage [This is a small program you need to put in your search path to build kernel U-Boot images]
-rwxr-xr-x 1 piet tensilica 635339 2009-12-07 19:40 u-boot [Started with xt-gdb to bring up the 1st instance of a HiFi 2 U-Boot]
-rwxr-xr-x 1 piet tensilica 144944 2009-12-07 19:40 u-boot.bin [Loaded by the 1st instance of U-Boot, it's a HiFi2 version of u-boot that will be put in flash]
$
Unless you are using a U-Boot snapshot you need to build U-Boot for which you must have built the Buildroot toolchain for XTensa core. Set your PATH to point to the toolchain built using buildroot. For example:
$ export PATH="<workdir>/buildroot/build_xtensa_<cname>/staging_dir/usr/bin:$PATH"
where <cname> is the name of the Xtensa core variant you wish to build for (e.g., dc232b dc233c).
To build U-Boot, use the cloned git tree pulled above, you should be at the top level of the tree in the u-boot directory , then configure it for your board and Xtensa core variant as follows:
make distclean make <cname>_<board>_config
'dc232b'dc This should only take a few seconds. For example, to build U-boot for the 'xtav60' board and the older 'dc232b' core with the V2 MMU type:
$ cd u-boot $ make dc232b_xtav60_config
or for the new 'dc233c' core with the new V3 MMU type:
$ make dc233c_xtav60_config
or for a 'xtav200' board type with the new 'dc233c' core type:
$ make dc233c_xtav110_config
or for a 'xtav200' board type with the new 'dc233c' core type:
$ make dc233c_xtav200_config
or for the snapshot_2+SMP branch you can also build U-Boot for the HiFi 2 core:
$ make test_mmuhifi_c3_xtav200_config [NOTE: You can skip this step with the the HiFi-2 snapshot_2+SMP branch; binaries are pre-built]
Only boards and core variants currently supported in the tree can be built out of the box. Headers for supported cores can be found in the tree under include/asm-xtensa/variant-<cname>. The core specific headers are described in the doc/README.xtensa file. To support a new core, these headers must be copied from the overlay in the same way as for the linux kernel.
After the configuration step, to actually build U-Boot, simply:
$ make all [NOTE: You can skip this step with the the HiFi-2 snapshot_2+SMP branch; binaries are pre-built]
This will take a quite a few minutes.
This is likely a good time to copy mkimage to your ${HOME}/bin directory for later use while building the Linux kernel. The mkimage program was just built in the tool directory by the above make all.
$ cd tools $ cp mkimage ~/bin [NOTE: mkimage should be in your search PATH while building the Linux kernel]
Next, start xt-gdb and load u-boot from the top of the git repository:
$ xt-gdb -n [NOTE: Even with the HiFi 2 snapshot_2+SMP branch you still may have to put U-Boot on the board] (xt-gdb) file u-boot (xt-gdb) if V3_MMU (xt-gdb) target remote localhost:20000 0 (xt-gdb) else (xt-gdb) target remote localhost:20000 0XD0000000 (xt-gdb) end (xt-gdb) reset (xt-gdb) load (xt-gdb) break panic (xt-gdb) continue
Hopefully U-Boot will start, and display on the LCD in the case of a LX60.
U-Boot 50.00 Mhz
Often you will be starting with the boards flash in an unknown state and it's best to unprotect and erase the entire flash. Just type protect off all followed by erase all:
U-Boot> protect off all Un-Protect Flash Bank # 1 ................................................................................................................................... done U-Boot> erase all Erase Flash Bank # 1 .......................................................................................................... Flash erase timeout at address f8d40000 da0 Flash erase error at address f8d40000 ........................ done U-Boot>
The timeout and error messages are likley just warning messages and you board has been erased. You can see that with the flash info command flinfo. Below is an example with a LX200 board, which has a much larger flash than the smaller LX60:
U-Boot> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 16 MB in 131 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 64 bytes
Sector Start Addresses:
F8000000 E F8020000 E F8040000 E F8060000 E F8080000 E
F80A0000 E F80C0000 E F80E0000 E F8100000 E F8120000 E
F8140000 E F8160000 E F8180000 E F81A0000 E F81C0000 E
F81E0000 E F8200000 E F8220000 E F8240000 E F8260000 E
F8280000 E F82A0000 E F82C0000 E F82E0000 E F8300000 E
F8320000 E F8340000 E F8360000 E F8380000 E F83A0000 E
F83C0000 E F83E0000 E F8400000 E F8420000 E F8440000 E
F8460000 E F8480000 E F84A0000 E F84C0000 E F84E0000 E
F8500000 E F8520000 E F8540000 E F8560000 E F8580000 E
F85A0000 E F85C0000 E F85E0000 E F8600000 E F8620000 E
F8640000 E F8660000 E F8680000 E F86A0000 E F86C0000 E
F86E0000 E F8700000 E F8720000 E F8740000 E F8760000 E
F8780000 E F87A0000 E F87C0000 E F87E0000 E F8800000 E
F8820000 E F8840000 E F8860000 E F8880000 E F88A0000 E
F88C0000 E F88E0000 E F8900000 E F8920000 E F8940000 E
F8960000 E F8980000 E F89A0000 E F89C0000 E F89E0000 E
F8A00000 E F8A20000 E F8A40000 E F8A60000 E F8A80000 E
F8AA0000 E F8AC0000 E F8AE0000 E F8B00000 E F8B20000 E
F8B40000 E F8B60000 E F8B80000 E F8BA0000 E F8BC0000 E
F8BE0000 E F8C00000 E F8C20000 E F8C40000 E F8C60000 E
F8C80000 E F8CA0000 E F8CC0000 E F8CE0000 E F8D00000 E
F8D20000 E F8D40000 E F8D60000 E F8D80000 E F8DA0000 E
F8DC0000 E F8DE0000 E F8E00000 E F8E20000 E F8E40000 E
F8E60000 E F8E80000 E F8EA0000 E F8EC0000 E F8EE0000 E
F8F00000 E F8F20000 E F8F40000 E F8F60000 E F8F80000 E
F8FA0000 E F8FC0000 E F8FE0000 E F8FE8000 E F8FF0000 E
F8FF8000 E
U-Boot>
The new LX110 looks very similar to the LX200, also with with 16Mb of Flash:
U-Boot> flinfo
Bank # 1: CFI conformant FLASH (8 x 8) Size: 16 MB in 128 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 32 bytes
Sector Start Addresses:
F8000000 E F8020000 E F8040000 E F8060000 E F8080000 E
F80A0000 E F80C0000 E F80E0000 E F8100000 E F8120000 E
F8140000 E F8160000 E F8180000 E F81A0000 E F81C0000 E
F81E0000 E F8200000 E F8220000 E F8240000 E F8260000 E
F8280000 E F82A0000 E F82C0000 E F82E0000 E F8300000 E
F8320000 E F8340000 E F8360000 E F8380000 E F83A0000 E
F83C0000 E F83E0000 E F8400000 E F8420000 E F8440000 E
F8460000 E F8480000 E F84A0000 E F84C0000 E F84E0000 E
F8500000 E F8520000 E F8540000 E F8560000 E F8580000 E
F85A0000 E F85C0000 E F85E0000 E F8600000 E F8620000 E
F8640000 E F8660000 E F8680000 E F86A0000 E F86C0000 E
F86E0000 E F8700000 E F8720000 E F8740000 E F8760000 E
F8780000 E F87A0000 E F87C0000 E F87E0000 E F8800000 E
F8820000 E F8840000 E F8860000 E F8880000 E F88A0000 E
F88C0000 E F88E0000 E F8900000 E F8920000 E F8940000 E
F8960000 E F8980000 E F89A0000 E F89C0000 E F89E0000 E
F8A00000 E F8A20000 E F8A40000 E F8A60000 E F8A80000 E
F8AA0000 E F8AC0000 E F8AE0000 E F8B00000 E F8B20000 E
F8B40000 E F8B60000 E F8B80000 E F8BA0000 E F8BC0000 E
F8BE0000 E F8C00000 E F8C20000 E F8C40000 E F8C60000 E
F8C80000 E F8CA0000 E F8CC0000 E F8CE0000 E F8D00000 E
F8D20000 E F8D40000 E F8D60000 E F8D80000 E F8DA0000 E
F8DC0000 E F8DE0000 E F8E00000 E F8E20000 E F8E40000 E
F8E60000 E F8E80000 E F8EA0000 E F8EC0000 E F8EE0000 E
F8F00000 E F8F20000 E F8F40000 E F8F60000 E F8F80000 E
F8FA0000 E F8FC0000 E F8FE0000 E
Now set your preliminary U-Boot environment variables to point to your TFTP server so we can download yet another copy of U-Boot. At Tensilica we use a machine in the RTOS group called rtos-lab2. Folks using the SMP HiFi 2 Development Board likely have set up their workstation with a TFTP server.
U-Boot> setenv serverip 192.168.11.78 rtos-lab2
or
U-Boot> setenv serverip 192.168.11.55 pdelaney_fc9
U-Boot> setenv ipaddr 192.168.11.95 I/P address of RTOS5, Piet's LX60; MAC: 00:05:C2:13:6f:0a
U-Boot> setenv bootfile u-boot.bin U-Boot> saveenv Saving Environment to Flash... .... done Un-Protected 4 sectors Erasing Flash... .... done Erased 4 sectors Writing to Flash... done .... done Protected 4 sectors U-Boot>
Next, download u-boot.bin from the tftp server using the info we just entered into U-Boot's enviroment variables.
Here for example is the case for a LX60 running the HiFi-2 Bitstream with the older V2 MMU. Note that it starts up
in the D-gazillion (0XD0000000) region:
U-Boot> tftpboot TFTP from server 192.168.11.78; our IP address is 192.168.11.95 Filename 'u-boot.bin'. Load address: 0xd2000000 Loading: T ######## done Bytes transferred = 107592 (1a448 hex)
For the V3 MMU U-Boot is loaded from host pdelaney_fc9 into memory with virtual == physical. Here is a DC233L, with V3 MMU, example:
U-Boot> tftpboot Using open_ethernet device TFTP from server 192.168.11.55; our IP address is 192.168.11.95 Filename 'u-boot.bin'. Load address: 0x2000000 Loading: T ######## done Bytes transferred = 109964 (1ad8c hex) U-Boot>
Now things get a bit tricky here for the LX60. The FLASH has Two sizes of Flash Sectors. The first 8 sectors are small 0x2000 (8KB) and apparently intended for parameters. The rest of the 4MB flash is composed of larger 0x10000 (64KB) sectors. Our code doesn't differentiate between the sectors and the LX60 hardware is going to map 0XF800,0000 to 0XFE00,0000 so this makes us use of all 8 of the 8KB sectors and the 1st 64KB sector at F8010000. So we are going to flash up to F801FFFF below.
On a LX200 we have much more space and can easily fit a version of U-boot that has been compiled without optimization, make debugging much easier.
So in this case the image is a bit larger, but relatively similar to the LX60 (2 sectors):
U-Boot> tftpboot Using open_ethernet device TFTP from server 192.168.11.78; our IP address is 192.168.11.95 Filename 'u-boot.bin'. Load address: 0xd2000000 Loading: ############### done Bytes transferred = 205852 (3241c hex) U-Boot>
On a LX110 we have less memory than an LX60, but FLASH sectors like the LX200. It turns out that the u-boot image compiled with optimization is just a bit larger than 1 sector, so like the LX200 we will need to write u-boot into two sectors. Here's and example tftpboot of U-Bot for the LX110:
U-Boot> tftpboot Using open_ethernet device TFTP from server 192.168.11.55; our IP address is 192.168.11.95 Filename 'u-boot.bin'. Load address: 0x2000000 Loading: ########## done Bytes transferred = 144956 (2363c hex) U-Boot>
Note that for both the LX200 and the LX60 that the image size, (3241c hex) in this case, is a bit less than 0x40000 or 10 sectors, so turn off protection on the 1st 11 sectors and erase the current contents.
On KC705 you do this:
U-Boot> tftp tensilica/u-boot.bin.test_kc705
ethoc
Using ETHOC-0 device
TFTP from server 192.168.11.1; our IP address is 192.168.11.2
Filename 'tensilica/u-boot.bin.test_kc705'.
Load address: 0x2000000
Loading: #########
691.4 KiB/s
done
Bytes transferred = 126050 (1ec62 hex)
For the LX60 you do this:
U-Boot> protect off F8000000 F801FFFF
... done
Un-Protected 9 sectors
U-Boot> erase F8000000 F801FFFF
erase F8000000 F801FFFF
... done
Erased 9 sectors
U-Boot>
For the LX200 and the LX110 the starting address (F8000000) is the same as with the LX60 but the last address (F803FFFF) is 'twice' as high:
U-Boot> protect off F8000000 F803FFFF ... done Un-Protected 2 sectors U-Boot> erase F8000000 F803FFFF Erased 2 sectors U-Boot>
For the KC705 the starting address is (F6000000) and the the reserved area is 8 Megabytes, with the last address of (F67fFFFF). There's no need to unprotect areas that you're not going to use though:
U-Boot> protect off F6000000 +20000 . done Un-Protected 1 sectors U-Boot> erase F6000000 +20000 Erased 1 sectors U-Boot>
Now copy the the image of u-boot.bin in memory to the flash. For the XL60 with the OLD V2 MMU you copy 0x20000
bytes from 0xd2000000 to 0XF8000000:
U-Boot> cp.b d2000000 F8000000 20000 Copy to Flash... done
For the LX60 with the NEW V3 MMU you copy 0x20000 bytes from 0x2000000 to F8000000:
U-Boot> cp.b 2000000 F8000000 20000 Copy to Flash... done
For the LX200 you copy 0x40000 bytes from 0xd2000000 to 0XF8000000...0XF803FFFF:
U-Boot> cp.b d2000000 F8000000 40000 Copy to Flash... done
For the LX110 with a V3-MMU you copy 0x40000 bytes from 0x2000000 to F8000000:
U-Boot> cp.b 2000000 F8000000 40000 Copy to Flash... done
For the KC705 with the V3 MMU you copy 0x20000 bytes from 0x2000000 to F6000000:
U-Boot> cp.b 2000000 F6000000 20000 Copy to Flash... done
Finally we protect these sectors so that U-Boot isn't easily erased by accident.
Below is what it looks like on a LX60 with the New V3 MMU with a subsequent display of the flash info:
U-Boot> cp.b 2000000 F8000000 2000
Copy to Flash... done
U-Boot> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 4 MB in 71 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x2257
Erase timeout: 8192 ms, write timeout: 1 ms
Sector Start Addresses:
F8000000 F8002000 F8004000 F8006000 F8008000
F800A000 F800C000 F800E000 F8010000 F8020000 E
F8030000 E F8040000 E F8050000 E F8060000 E F8070000 E
F8080000 E F8090000 E F80A0000 E F80B0000 E F80C0000 E
F80D0000 E F80E0000 E F80F0000 E F8100000 E F8110000 E
F8120000 E F8130000 E F8140000 E F8150000 E F8160000 E
F8170000 E F8180000 E F8190000 E F81A0000 E F81B0000 E
F81C0000 E F81D0000 E F81E0000 E F81F0000 E F8200000 E
F8210000 E F8220000 E F8230000 E F8240000 E F8250000 E
F8260000 E F8270000 E F8280000 E F8290000 E F82A0000 E
F82B0000 E F82C0000 E F82D0000 E F82E0000 E F82F0000 E
F8300000 E F8310000 E F8320000 E F8330000 E F8340000 E
F8350000 E F8360000 E F8370000 E F8380000 E F8390000 E
F83A0000 E F83B0000 E F83C0000 E F83D0000 E F83E0000
F83F0000 RO
U-Boot> protect on F8000000 F801FFFF
.......... done
Protected 9 sectors
U-Boot>
U-Boot> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 4 MB in 71 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x2257
Erase timeout: 8192 ms, write timeout: 1 ms
Sector Start Addresses:
F8000000 RO F8002000 RO F8004000 RO F8006000 RO F8008000 RO
F800A000 RO F800C000 RO F800E000 RO F8010000 RO F8020000 E
F8030000 E F8040000 E F8050000 E F8060000 E F8070000 E
F8080000 E F8090000 E F80A0000 E F80B0000 E F80C0000 E
F80D0000 E F80E0000 E F80F0000 E F8100000 E F8110000 E
F8120000 E F8130000 E F8140000 E F8150000 E F8160000 E
F8170000 E F8180000 E F8190000 E F81A0000 E F81B0000 E
F81C0000 E F81D0000 E F81E0000 E F81F0000 E F8200000 E
F8210000 E F8220000 E F8230000 E F8240000 E F8250000 E
F8260000 E F8270000 E F8280000 E F8290000 E F82A0000 E
F82B0000 E F82C0000 E F82D0000 E F82E0000 E F82F0000 E
F8300000 E F8310000 E F8320000 E F8330000 E F8340000 E
F8350000 E F8360000 E F8370000 E F8380000 E F8390000 E
F83A0000 E F83B0000 E F83C0000 E F83D0000 E F83E0000
F83F0000 RO
U-Boot>
For the LX110 with the V3-MMU here's what the flash info looks like after we protect the first two sectors with U-Boot copied to it:
U-Boot> protect on F8000000 F803FFFF
Protected 2 sectors
U-Boot> flinfo
Bank # 1: CFI conformant FLASH (8 x 8) Size: 16 MB in 128 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 32 bytes
Sector Start Addresses:
F8000000 RO F8020000 RO F8040000 E F8060000 E F8080000 E
F80A0000 E F80C0000 E F80E0000 E F8100000 E F8120000 E
F8140000 E F8160000 E F8180000 E F81A0000 E F81C0000 E
F81E0000 E F8200000 E F8220000 E F8240000 E F8260000 E
F8280000 E F82A0000 E F82C0000 E F82E0000 E F8300000 E
F8320000 E F8340000 E F8360000 E F8380000 E F83A0000 E
F83C0000 E F83E0000 E F8400000 E F8420000 E F8440000 E
F8460000 E F8480000 E F84A0000 E F84C0000 E F84E0000 E
F8500000 E F8520000 E F8540000 E F8560000 E F8580000 E
F85A0000 E F85C0000 E F85E0000 E F8600000 E F8620000 E
F8640000 E F8660000 E F8680000 E F86A0000 E F86C0000 E
F86E0000 E F8700000 E F8720000 E F8740000 E F8760000 E
F8780000 E F87A0000 E F87C0000 E F87E0000 E F8800000 E
F8820000 E F8840000 E F8860000 E F8880000 E F88A0000 E
F88C0000 E F88E0000 E F8900000 E F8920000 E F8940000 E
F8960000 E F8980000 E F89A0000 E F89C0000 E F89E0000 E
F8A00000 E F8A20000 E F8A40000 E F8A60000 E F8A80000 E
F8AA0000 E F8AC0000 E F8AE0000 E F8B00000 E F8B20000 E
F8B40000 E F8B60000 E F8B80000 E F8BA0000 E F8BC0000 E
F8BE0000 E F8C00000 E F8C20000 E F8C40000 E F8C60000 E
F8C80000 E F8CA0000 E F8CC0000 E F8CE0000 E F8D00000 E
F8D20000 E F8D40000 E F8D60000 E F8D80000 E F8DA0000 E
F8DC0000 E F8DE0000 E F8E00000 E F8E20000 E F8E40000 E
F8E60000 E F8E80000 E F8EA0000 E F8EC0000 E F8EE0000 E
F8F00000 E F8F20000 E F8F40000 E F8F60000 E F8F80000 E
F8FA0000 E F8FC0000 E F8FE0000 RO
U-Boot> help
Below is what it looks like on a LX200 with the V2 MMU with a subsequent display of the flash info.
Notice that the Flash Sectors are 10X as large on the LX200:
U-Boot> protect on F8000000 F803FFFF .. done Protected 2 sectors U-Boot> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 16 MB in 131 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 64 bytes
Sector Start Addresses:
F8000000 RO F8020000 RO F8040000 E F8060000 E F8080000 E
F80A0000 E F80C0000 E F80E0000 E F8100000 E F8120000 E
F8140000 E F8160000 E F8180000 E F81A0000 E F81C0000 E
F81E0000 E F8200000 E F8220000 E F8240000 E F8260000 E
F8280000 E F82A0000 E F82C0000 E F82E0000 E F8300000 E
F8320000 E F8340000 E F8360000 E F8380000 E F83A0000 E
F83C0000 E F83E0000 E F8400000 E F8420000 E F8440000 E
F8460000 E F8480000 E F84A0000 E F84C0000 E F84E0000 E
F8500000 E F8520000 E F8540000 E F8560000 E F8580000 E
F85A0000 E F85C0000 E F85E0000 E F8600000 E F8620000 E
F8640000 E F8660000 E F8680000 E F86A0000 E F86C0000 E
F86E0000 E F8700000 E F8720000 E F8740000 E F8760000 E
F8780000 E F87A0000 E F87C0000 E F87E0000 E F8800000 E
F8820000 E F8840000 E F8860000 E F8880000 E F88A0000 E
F88C0000 E F88E0000 E F8900000 E F8920000 E F8940000 E
F8960000 E F8980000 E F89A0000 E F89C0000 E F89E0000 E
F8A00000 E F8A20000 E F8A40000 E F8A60000 E F8A80000 E
F8AA0000 E F8AC0000 E F8AE0000 E F8B00000 E F8B20000 E
F8B40000 E F8B60000 E F8B80000 E F8BA0000 E F8BC0000 E
F8BE0000 E F8C00000 E F8C20000 E F8C40000 E F8C60000 E
F8C80000 E F8CA0000 E F8CC0000 E F8CE0000 E F8D00000 E
F8D20000 E F8D40000 E F8D60000 E F8D80000 E F8DA0000 E
F8DC0000 E F8DE0000 E F8E00000 E F8E20000 E F8E40000 E
F8E60000 E F8E80000 E F8EA0000 E F8EC0000 E F8EE0000 E
F8F00000 E F8F20000 E F8F40000 E F8F60000 E F8F80000 E
F8FA0000 E F8FC0000 E F8FE0000 RO F8FE8000 RO F8FF0000 RO
F8FF8000 RO
U-Boot>
Note that the U-Boot saveenv command Erased and protected the last four sectors of this LX200.
Now move Boot Select DIP switch to the ON position. Next, power cycle the board. On the LX60 you should see U-boot in the LCD display.
The LX60 with the new V3 MMU the serial console should print something like the following:
U-Boot 2009.08-dirty (Sep 10 2010 - 18:23:26) CPU: Xtensa dc233c at 50.00 MHz Board: XT-AV60: Avnet board + Xilinx LX60 FPGA + Tensilica bitstream SysRAM: 64 MB Flash: 4 MB In: serial Out: serial Err: serial MAC: 00:50:C2:13:6f:0a IP: 192.168.11.95 open_ethernet U-Boot>
On the LX110 with the new V3 MMU the serial console should print something like the following:
U-Boot 2009.08-dirty (Nov 15 2010 - 23:04:45) CPU: Xtensa dc233c at 50.00 MHz Board: XT-AV110: Avnet board + Xilinx LX110 FPGA + Tensilica bitstream SysRAM: 48 MB Flash: 16 MB In: serial Out: serial Err: serial MAC: 00:50:C2:13:6f:00 IP: 192.168.11.95 open_ethernet U-Boot>
On the LX200, shown below with the old V2 MMU, you should see something like the following. In this case we also show the flash info command, flinfo, being invoked just after booting U-Boot:
U-Boot 2009.08-dirty (Nov 15 2010 - 23:04:45)
CPU: Xtensa test_mmuhifi_c3 at 41.6777 MHz
Board: XT-AV200: Avnet board + Xilinx LX200 FPGA + Tensilica bitstream
SysRAM: 96 MB
Flash: 16 MB
In: serial
Out: serial
Err: serial
MAC:
IP: 192.168.11.95
U-Boot>
U-Boot> flinfo
Bank # 1: CFI conformant FLASH (16 x 16) Size: 16 MB in 131 Sectors
Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x18
Erase timeout: 4096 ms, write timeout: 1 ms
Buffer write timeout: 2 ms, buffer size: 64 bytes
Sector Start Addresses:
F8000000 RO F8020000 RO F8040000 E RO F8060000 E RO F8080000 E RO
F80A0000 E RO F80C0000 E RO F80E0000 E RO F8100000 E RO F8120000 E RO
F8140000 E RO F8160000 E RO F8180000 E RO F81A0000 E RO F81C0000 E RO
F81E0000 E RO F8200000 E RO F8220000 E RO F8240000 E RO F8260000 E RO
F8280000 E RO F82A0000 E RO F82C0000 E RO F82E0000 E RO F8300000 E RO
F8320000 E RO F8340000 E RO F8360000 E RO F8380000 E RO F83A0000 E RO
F83C0000 E RO F83E0000 E RO F8400000 E RO F8420000 E RO F8440000 E RO
F8460000 E RO F8480000 E RO F84A0000 E RO F84C0000 E RO F84E0000 E RO
F8500000 E RO F8520000 E RO F8540000 E RO F8560000 E RO F8580000 E RO
F85A0000 E RO F85C0000 E RO F85E0000 E RO F8600000 E RO F8620000 E RO
F8640000 E RO F8660000 E RO F8680000 E RO F86A0000 E RO F86C0000 E RO
F86E0000 E RO F8700000 E RO F8720000 E RO F8740000 E RO F8760000 E RO
F8780000 E RO F87A0000 E RO F87C0000 E RO F87E0000 E RO F8800000 E RO
F8820000 E RO F8840000 E RO F8860000 E RO F8880000 E RO F88A0000 E RO
F88C0000 E RO F88E0000 E RO F8900000 E RO F8920000 E RO F8940000 E RO
F8960000 E RO F8980000 E RO F89A0000 E RO F89C0000 E RO F89E0000 E RO
F8A00000 E RO F8A20000 E RO F8A40000 E RO F8A60000 E RO F8A80000 E RO
F8AA0000 E RO F8AC0000 E RO F8AE0000 E RO F8B00000 E RO F8B20000 E RO
F8B40000 E RO F8B60000 E RO F8B80000 E RO F8BA0000 E RO F8BC0000 E RO
F8BE0000 E RO F8C00000 E RO F8C20000 E RO F8C40000 E RO F8C60000 E RO
F8C80000 E RO F8CA0000 E RO F8CC0000 E RO F8CE0000 E RO F8D00000 E RO
F8D20000 E RO F8D40000 E RO F8D60000 E RO F8D80000 E RO F8DA0000 E RO
F8DC0000 E RO F8DE0000 E RO F8E00000 E RO F8E20000 E RO F8E40000 E RO
F8E60000 E RO F8E80000 E RO F8EA0000 E RO F8EC0000 E RO F8EE0000 E RO
F8F00000 E RO F8F20000 E RO F8F40000 E RO F8F60000 E RO F8F80000 E RO
F8FA0000 E RO F8FC0000 E RO F8FE0000 RO F8FE8000 RO F8FF0000 RO
F8FF8000 RO
U-Boot>
Note that the 1st two sectors with U-Boot saved in them came up as not being erased (E) but that all sectors came up Read Only (RO).
Same with the last four sectors that the U-Boot saveenv command Erased. This is likely a bug on the LX200 boards with some preliminary investigation.
We will be discussing this with the U-Boot developers sometime in the future prior to pushing our U-boot changes upstream.
If U-Boot fails to boot ya might try making sure your U-Boot serverip environment variable matches the address of the tftp server where
you have copied your u-boot.bin file to and comparing the bits in the flash that got mapped to 0xfe00,0000 to what in the file:
u-boot]$ od -t x4 u-boot.bin | more .0000000 00000206 fe000040 ffffffff a0fffe21 .0000020 00000002 fe01ad14 fe01ad8c 03f95030 .0000040 03f9aa78 04000000 00040003 03f8147c .0000060 03f81418 00000000 00000000 00000000 .0000100 5300000c 13a00013 4800130c 13493013 .0000120 0c130200 13e62032 22002010 a03200a0 .0000140 1d837680 82037282 72822372 63728243 .0000160 72007272 72720872 18727210 2201d222 .0000200 020c80c2 3d80a032 1d8376f0 d20372d2 .0000220 72d22372 6372d243 f20072f2 72f20872 .0000240 1872f210 2201d222 200080c2 ffd92100 .0000260 37ffda31 02481d12 22681258 145722cb .0000300 ee1467f1 664b0678 444b0479 06f43457 .0000320 0000fff8 31ffd221 4320ffd2 40443bc0 .0000340 84764142 4b020903 32020c22 837680a0 .0000360 04728211 82247282 72824472 01d22264 .0000400 1180c222 c821ffc8 13e620ff 41002010 .0000420 04d0ffc7 ffc64100 fffffd86 1049c500 .0000440 e52049d5 49f53049 00003400 00000000 .0000460 00000000 00000000 00000000 00000000 . .(gdb) x/100x 0xfe000000 .0xfe000000 <_ResetVector>: 0x00000206 0xfe000040 0xffffffff 0xa0fffe21 .0xfe000010 <_ResetVector+16>: 0x00000002 0xfe01ad14 0xfe01ad8c 0x03f95030 .0xfe000020 <_ResetVector+32>: 0x03f9aa78 0x04000000 0x00040003 0x03f8147c .0xfe000030 <_ResetVector+48>: 0x03f81418 0x00000000 0x00000000 0x00000000 .0xfe000040 <_start>: 0x5300000c 0x13a00013 0x4800130c 0x13493013 .0xfe000050 <_start+16>: 0x0c130200 0x13e62032 0x22002010 0xa03200a0 .0xfe000060 <_start+32>: 0x1d837680 0x82037282 0x72822372 0x63728243 .0xfe000070 <_start+48>: 0x72007272 0x72720872 0x18727210 0x2201d222 .0xfe000080 <_start+64>: 0x020c80c2 0x3d80a032 0x1d8376f0 0xd20372d2 .0xfe000090 <_start+80>: 0x72d22372 0x6372d243 0xf20072f2 0x72f20872 .0xfe0000a0 <_start+96>: 0x1872f210 0x2201d222 0x200080c2 0xffd92100 .0xfe0000b0 <_start+112>: 0x37ffda31 0x02481d12 0x22681258 0x145722cb .0xfe0000c0 <_start+128>: 0xee1467f1 0x664b0678 0x444b0479 0x06f43457 .0xfe0000d0 <_start+144>: 0x0000fff8 0x31ffd221 0x4320ffd2 0x40443bc0 .0xfe0000e0 <_start+160>: 0x84764142 0x4b020903 0x32020c22 0x837680a0 .0xfe0000f0 <_start+176>: 0x04728211 0x82247282 0x72824472 0x01d22264 .0xfe000100 <_start+192>: 0x1180c222 0xc821ffc8 0x13e620ff 0x41002010 .0xfe000110 <_reset+1>: 0x04d0ffc7 0xffc64100 0x00fffd86 0x1049c500 .0xfe000120: 0xe52049d5 0x49f53049 0x00003400 0x00000000 .0xfe000130: 0x00000000 0x00000000 0x00000000 0x00000000 .(gdb)
Further details on U-Boot in general are in the generic README at the top of the U-Boot tree. Details specific to the Xtensa architecture are in doc/README.xtensa. Details specific to a board are in board[/<family>]/<board>/README (for example board/avnet/xtav60/README).