Supported Processor Configurations: Difference between revisions

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m (drop highmem and aliasing cache notes as both are resolved now)
 
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= Software Recommendations =
== 128 MB RAM Limit ==
Kernel highmem support has not yet been implemented in the main kernel tree, thus restricting generally usable RAM to the first 128 MB (starting from physical address zero).  Implementing kernel highmem support should release this limitation, but it isn't yet clear whether an implementation is practical in the presence of cache aliasing (caches larger than 4 x N kB, for an N-way set-associative cache) on RB-200x release or earlier Tensilica processors.
= Hardware Recommendations =
= Hardware Recommendations =


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Tensilica's PIF Bridges all support this, but if you are using other bridges, this implementation should be verified.
Tensilica's PIF Bridges all support this, but if you are using other bridges, this implementation should be verified.
== Large RAM with Large Caches ==
Tensilica asks to please contact Tensilica support if you are planning to use or build a linux based system that may require more than 128 MB of main RAM for an Xtensa processor configured with large caches (cache size > 4*N kB, for an N-way set associative cache). There are some system limitations that should be evaluated before proceeding.

Latest revision as of 23:31, 15 October 2014

Hardware Recommendations

This section contains recommendations, notes, limitations and requirements for the development of hardware systems using Linux-Xtensa. They are oriented more towards hardware designer when they create a new Xtensa processor configuration or design an SOC with Xtensa processors.

MMU

Processor configurations that run Linux should always include the MMU feature. Although Linux also supports MMU-less processors, it is not very well tested and has a lot of pitfalls. If the overhead of an MMU is too big, an alternative open or closed source operating system should be considered.

Atomic Memory Access Support

For future compatibility with Linux kernel releases for the Xtensa architecture, please include support for the atomic load-conditional-store S32C1I instruction when designing your memory system. The memory system must provide for the atomic update of a memory location by holding off the load until all other transactions are complete, and holding off any other transactions once the atomic operation has started until it has finished.

Tensilica's PIF Bridges all support this, but if you are using other bridges, this implementation should be verified.

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