KnownIssues: Difference between revisions

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= Known Kernel Issues and Limitations =


== Hardware System Limitations ==
This section contains recommendations, notes, limitations, and requirements for the development of hardware systems using Xtensa processors running Linux.
'''Recommendations'''
For future compatibility with Linux kernel releases for the Xtensa architecture, please include support for the atomic load-conditional-store S32C1I instruction when designing your memory system. The memory system must provide for the atomic update of a memory location by holding off the load until all other transactions are complete, and holding off any other transactions once the atomic operation has started until it has finished.  Tensilica's PIF Bridges all support this but if you are using other bridges this implementation should be verified.
Please contact Tensilica support if planning to use or build a linux based system that may require more than 128 MB of main RAM for an Xtensa processor configured with large caches (cache size > 4*N kB, for an N-way set associative cache). There are some system limitations that should be evaluated before proceeding.
== Software Limitations ==
This section contains recommendations, notes, limitations, and requirements for the development of software on systems using Xtensa processors running Linux.
Eventually all these should be duly reported and tracked in
the [http://bugs.linux-xtensa.org Mantis bug tracker].
For the time being, here are some of the main known issues (this is by no means an exhaustive list!).
=== 128 MB RAM Limit ===
Kernel highmem support has not yet been implemented, thus restricting generally usable RAM to the first 128 MB (starting from physical address zero).  Implementing kernel highmem support should release this limitation, but it isn't yet clear whether an implementation is practical in the presence of cache aliasing (caches larger than 4 x N kB, for an N-way set-associative cache) on RB-200x release or earlier Tensilica processors.
=== Kernel loadable modules using FLIX with L32R ===
The kernel module loader (for the Xtensa architecture) supports only the limited set of relocations needed for module loading.  This includes, for example, relocation of literals referenced by L32R instructions.  This loader is not given specific information about any custom TIE configured in the processor, and thus is currently not able to relocate L32R instructions encoded in a FLIX bundle.
To ensure kernel modules load properly, they need to avoid L32R instructions within FLIX instruction bundles.
Existing kernel code does not generate such instructions, so it is not susceptible.
However, it is possible to generate FLIX instructions using assembly code, or using the Tensilica XCC compiler.  In the case of assembly code, simply avoid using L32R or MOVI instructions within a FLIX instruction bundle, unless a MOVI is known to fit without expanding ("relaxing") into an L32R instruction.  In the case of XCC, pass the -mno-flix to the compiler (xt-xcc) to avoid generating FLIX bundles.

Latest revision as of 18:59, 11 November 2013

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