Supported Processor Configurations

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The following list is oriented more towards hardware designer when they create a new Xtensa processor configuration. They are recommendations for various processor options that can be selected when defining the processor.


Processor configurations to run Linux should always include MMU support. Although Linux also supports MMU-less processors, it is not very well tested and has a lot of pitfalls. If the overhead of an MMU is too big, an alternative open or closed source operating system should be considered.

Atomic Memory Access Support

For future compatibility with Linux kernel releases for the Xtensa architecture, please include support for the atomic load-conditional-store S32C1I instruction when designing your memory system. The memory system must provide for the atomic update of a memory location by holding off the load until all other transactions are complete, and holding off any other transactions once the atomic operation has started until it has finished.

Tensilica's PIF Bridges all support this, but if you are using other bridges, this implementation should be verified.

Large RAM with Large Caches

Tensilica asks to please contact Tensilica support if you are planning to use or build a linux based system that may require more than 128 MB of main RAM for an Xtensa processor configured with large caches (cache size > 4*N kB, for an N-way set associative cache). There are some system limitations that should be evaluated before proceeding.