Supported Processor Configurations
Hardware System Limitations
This page contains recommendations, notes, limitations, and requirements for the development of hardware systems using Xtensa processors running Linux.
Atomic Memory Access Support
For future compatibility with Linux kernel releases for the Xtensa architecture, please include support for the atomic load-conditional-store S32C1I instruction when designing your memory system. The memory system must provide for the atomic update of a memory location by holding off the load until all other transactions are complete, and holding off any other transactions once the atomic operation has started until it has finished.
Tensilica's PIF Bridges all support this, but if you are using other bridges, this implementation should be verified.
Large RAM with Large Caches
Tensilica asks to please contact Tensilica support if you are planning to use or build a linux based system that may require more than 128 MB of main RAM for an Xtensa processor configured with large caches (cache size > 4*N kB, for an N-way set associative cache). There are some system limitations that should be evaluated before proceeding.