Instruction Set Simulators

From Linux/Xtensa
Revision as of 23:39, 13 April 2007 by Chris (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

Instruction Set Simulators (ISS) mimic the behavior of processors by simulating instructions, memory interface, and other I/O components. This allows developers to run and test their software long before real hardware becomes available. Functional simulators provide the best performance but lack the time consistency delivered by cycle-accurate simulators. These simulate the processor pipeline and external components synchronized to a virtual clock. Although this overhead reduces their performance, it can provide vital information to improve the implementation of algorithms.

Tensilica ISS

Tensilica offers a commercial cycle-accurate simulator and a functional simulator for the Xtensa processor architecture. Please, visit Tensilica's website for further information.

The simulator (xt-iss) simply takes an ELF file as its argument and starts simulating instructions from the START address as defined in the ELF header. The option --turbo invokes the functional simulator TurboXim.

xt-iss [--turbo] Image.elf