Instruction Set Simulators: Difference between revisions
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[http://www.tensilica.com/ Tensilica] offers a commercial cycle-accurate simulator and a functional simulator for the Xtensa processor architecture. Please, visit [http://www.tensilica.com/ Tensilica's] website for further information. | [http://www.tensilica.com/ Tensilica] offers a commercial cycle-accurate simulator and a functional simulator for the Xtensa processor architecture. Please, visit [http://www.tensilica.com/ Tensilica's] website for further information. | ||
The simulator (xt-iss) simply takes an ELF file as its argument and starts simulating instructions from the | The simulator (xt-iss) simply takes an ELF file as its argument and starts simulating instructions from the reset vector. The option <code>--turbo</code> invokes the (much faster) functional simulator TurboXim. | ||
xt-iss ''[--turbo]'' Image.elf | xt-iss ''[--turbo]'' Image.elf | ||
Latest revision as of 20:12, 8 October 2007
Instruction Set Simulators (ISS) mimic the behavior of processors by simulating instructions, memory interface, and other I/O components. This allows developers to run and test their software long before real hardware becomes available. Functional simulators provide the best performance but lack the time consistency delivered by cycle-accurate simulators. These simulate the processor pipeline and external components synchronized to a virtual clock. Although this overhead reduces their performance, it can provide vital information to improve the implementation of algorithms.
Tensilica ISS
Tensilica offers a commercial cycle-accurate simulator and a functional simulator for the Xtensa processor architecture. Please, visit Tensilica's website for further information.
The simulator (xt-iss) simply takes an ELF file as its argument and starts simulating instructions from the reset vector. The option --turbo invokes the (much faster) functional simulator TurboXim.
xt-iss [--turbo] Image.elf